std/embedded/chip/rp_pins

Library guide · API index and notation

This page is generated from the bundled library in this checkout. Signatures and adjacent source comments are reproduced below; the linked guide explains usage, storage, failures, and platform support.

import "std/embedded/chip/rp_pins"

Names used in signatures

Unqualified names denote this package’s types (including other source files in the same package), language built-ins, or generic parameters such as T. Qualified names use the import aliases below. These aliases belong to the library source; import a dependency yourself to use its alias in your program.

PIN_COUNT

Constant · Source

The GPIOs whose functions both chips share.

pub const PIN_COUNT: u32 = 30

I2C0

Constant · Source

The bus controllers, as Bank numbers them for its chip.

pub const I2C0: u32 = 0

I2C1

Constant · Source

pub const I2C1: u32 = 1

SPI0

Constant · Source

pub const SPI0: u32 = 2

SPI1

Constant · Source

pub const SPI1: u32 = 3

i2c_controller

Function · Source

The I2C controller, 0 or 1, that pins sda and scl form a bus on. Even pins carry SDA and odd pins SCL. GPIO 0 and 1, 4 and 5, and so on in steps of four belong to I2C0; GPIO 2 and 3, 6 and 7, and so on to I2C1. InvalidInput if the two pins cannot form a bus.

pub fn i2c_controller(sda: u32, scl: u32) -> u32!hal.Error

SpiPins

Struct · Source

The pins of an SPI bus, from spi_pins.

pub struct SpiPins {
    // The controller, 0 or 1.
    pub controller: u32
    // The receive pin, if the bus has one.
    pub rx: Option<u32>
    // Every pin of the bus, one bit each.
    pub mask: u32
}

spi_pins

Function · Source

The SPI bus that pins clock, tx, and rx (if any) form. GPIO n carries RX when n % 4 is 0, the clock when it is 2, and TX when it is 3. GPIO 0 to 7 and 16 to 23 belong to SPI0, GPIO 8 to 15 and 24 to 29 to SPI1. InvalidInput if the pins cannot form a bus.

pub fn spi_pins(clock: u32, tx: u32, rx: Option<u32>) -> SpiPins!hal.Error

Bank

Struct · Source

GPIO 0 to 29 and the bus controllers of one chip C, each handed out once and taken back by the release methods. C does what differs between the chips, with these methods, controller numbered as I2C0 to SPI1 above:

route(&mut self, pin: u32, function: u32, clear: u32, set: u32) connect the pin to FUNCSEL function, then clear the clear and set the set bits of its pad reset(&mut self, controller: u32) -> void!hal.Error pulse the controller’s reset and wait until it runs hold(&mut self, controller: u32) hold the controller in reset base(&self, controller: u32) -> usize the controller’s register block clock_hz(&self) -> u32 the frequency of the clock that feeds the controllers

pub struct Bank<C> {
    // Private implementation fields omitted.
}

Bank.new

Function · Source

SAFETY: C’s methods must do what the protocol above says, base must name the controller’s PL022 or DW_apb_i2c, and the bank must be the only user of GPIO 0 to 29’s control and pad registers, of the four controllers, and of their resets.

pub unsafe fn new(chip: C) -> Bank<C>

Requires an unsafe context. Follow the source safety preconditions and the linked guide before calling this API.

Bank.gpio

Function · Source

Claim pin number for the single-cycle I/O block. Returns its bit, for the chip’s GPIO registers. InvalidInput above GPIO 29, Busy if taken.

pub fn gpio(&mut self, number: u32) -> u32!hal.Error

Bank.release_gpio

Function · Source

Give back the GPIO with bit mask, from gpio, which the caller has stopped driving. The pin is disconnected until it is claimed again.

pub fn release_gpio(&mut self, mask: u32)

Bank.i2c

Function · Source

Claim pins sda and scl as an I2C bus with an SCL frequency of frequency_hz; see i2c_controller for the pins. InvalidInput if the two pins cannot form a bus or the frequency is out of range, Busy if a pin or the controller is taken. The pads’ pull-ups (about 50 kOhm) keep an idle bus high but are too weak for fast mode.

pub fn i2c(&mut self, sda: u32, scl: u32, frequency_hz: u32) -> designware_i2c.Bus!hal.Error

Bank.spi

Function · Source

Claim pins as an SPI bus in mode, clocked at the fastest rate up to frequency_hz; see spi_pins for the pins. Errors as for i2c.

pub fn spi(&mut self, clock: u32, tx: u32, rx: Option<u32>, mode: hal.SpiMode, frequency_hz: u32) -> pl022.Bus!hal.Error

Bank.release_i2c

Function · Source

Give back an I2C bus from i2c: its pins are disconnected, still pulled up so the bus stays idle, and its controller held in reset. The pins can then be claimed as GPIOs, for example to clock a stuck device free, and the bus claimed again.

pub fn release_i2c(&mut self, bus: designware_i2c.Bus)

Bank.release_spi

Function · Source

Give back an SPI bus from spi, as for release_i2c.

pub fn release_spi(&mut self, bus: pl022.Bus)